1. Field of the Invention
The present invention relates to a semiconductor memory device and its fabrication process.
2. Description of the Related Art
In NAND type non-volatile semiconductor memory device, bit lines and word lines are arranged to extend to intersect with each other. Memory cells are formed in each region in which one of the bit lines and one of the word lines intersects each other. A memory cell comprises a tunnel insulator film, a floating gate, inter-poly insulator film, and a control gate laminated in this order. STIs (Shallow Trench Isolation), comprising element isolation trenches and element isolation films, are formed between adjacent memory cells next to word line direction.
Silicon dioxide is one of the materials used for the element isolation film. As the distance between memory cells decrease with the design rule reduction, a parasitic capacitance between neighboring floating gates increases. It causes a cell interference problem between neighboring cells and leads to a mal-functioning of the device.
To reduce the parasitic capacitance and fix this problem, air gaps in STIs are proposed by using a poor coverage silicon oxide film for filling of the element isolation trenches.
With this structure, inter poly insulator films and control gate electrodes do not cover side walls of floating gate electrodes. That causes another problem of reducing a coupling ratio between floating gate electrodes and control gate electrodes.